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Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
FEATURES
* * * * * * * * * Selectable 12.5MHz to 200MHz range. Low phase noise output (@ 10kHz frequency offset, -140dBc/Hz for 17.664MHz, -132dBc/Hz for 35.328MHz, -125dBc/Hz for 155.52MHz). 4 CMOS outputs (in phase). 12 to 25MHz crystal input. No external load capacitor or varicap required. Wide pull range (+/-190 ppm) Selectable 1/2 to 8x frequency multiplier. 3.3V operation. Available in 14-SOP.
PIN CONFIGURATION (Top View)
VDD XIN XOUT SEL2^ SEL1^ VCON GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SEL0^ CLK4 CLK3 VDD CLK2 CLK1 GND
PLL 502-67
DESCRIPTIONS
The PLL502-67 is high performance and low phase noise VCXO IC chip. It provides phase noise performance as low as -140dBc at 1kHz offset (at 17.664MHz) and -125dBc at 1kHz offset at 155.52MHz by multiplying the input crystal frequency up to 8x. The wide pull range (+/- 190 ppm) and very low jitter makes this chip ideal for a wide range of applications, from xDSL to SONET/SDH and FEC. The chip accepts a low cost fundamental parallel resonant mode crystal from 12 to 25MHz.
^: Internal pull-up
BLOCK DIAGRAM
SEL CLK4 VCON XIN XOUT
Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop)
CLK3 CLK2 CLK1
PLL by-pass
PLL502-67
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 1
Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
FREQUENCY SELECTION TABLE
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Reserved Reserved Reserved Fin x 2 Fin / 2 Fin x 4 Fin x 8 No multiplication Selected Multiplier
Note: Internal pull-ups default SEL2, SEL1 and SEL0 to `1' if not connected
PIN DESCRIPTIONS
Name
XIN XOUT VCON GND CLK1, CLK2 CLK3, CLK4 SEL2 SEL1 SEL0 VDD
Pin number
2 3 6 7,8 9,10 12,13 4 5 14 1, 11
Type
I I I P O O I I I P Crystal in connector. Crystal out connector.
Description
Frequency control input (0.3V to 3.0V) GND. Output signal Output signal. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V VDD.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 2
Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
V DD VI VO TS TA TJ
MIN.
MAX.
7
UNITS
V V V C C C C kV
V SS -0.5 V SS -0.5 -65 -40
V DD +0.5 V DD +0.5 150 85 125 260 2
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR
SYMBOL
F XIN CL (xtal) C 0 /C 1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode At VCON = 1.65V AT cut AT cut
MIN.
12
TYP.
MAX.
25
UNITS
MHz pF
9 250 30
Note: Crystal Loading rating: 9pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 3
Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 2000 25
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V
MIN.
380 190
TYP.
10
MAX.
UNITS
ms ppm ppm
5 150
10
% ppm/V k kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Short Circuit Current
SYMBOL
IDD
CONDITIONS
4 outputs loaded at 18pF Fout = 17.664MHz Fout = 35.328MHz Fout < 141MHz
MIN.
TYP.
15 42 71
MAX.
30 60 80 3.47
UNITS
mA
VDD
3.13 50
V mA
5. AC Electrical Specifications PARAMETERS
Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Short Circuit Current 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 2.0V ~ 0.8V with 10 pF load 3.0V ~ 0.3V with 15pF load Measured @ 1.4V 45 2 50 50 2
SYMBOL
CONDITIONS
MIN.
12
TYP.
MAX.
25 1.5 5 1.5 5 55
UNITS
MHz
ns
% mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 4
Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
6. Jitter specifications PARAMETERS
Period jitter RMS
CONDITIONS
With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
FREQUENCY
17.664MHz 35.328MHz 155.52MHz
MIN.
TYP.
2.5 4 4.5 30 2.5
MAX.
5 7 9 60 4
UNITS
ps
Peak to Peak jitter Integrated jitter RMS
155.52MHz 155.52MHz
ps ps
7. Phase noise specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
17.664MHz 70.656MHz 155.52MHz
@10Hz
-60 -60 -60
@100Hz
-90 -90 -90
@1kHz
-112 -112 -112
@10kHz
-140 -127 -125
@100kHz
-150 -125 -123
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 5
Preliminary
PLL502-67
4 Outputs 12.5MHz - 200MHz Low Phase Noise Multiplier VCXO
PACKAGE INFORMATION
14 PIN Narrow SOIC ( mm )
SOIC Symbol A A1 B C D E H L e Min. 1.35 0.10 0.33 0.19 8.58 3.85 5.80 0.40 1.27 BSC B e Max. 1.75 0.25 0.51 0.25 8.69 3.97 6.20 1.27 A1 C L A D E H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL502-67 S C
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/20/03 Page 6

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